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TCN75
DS21490C-page 12
?2006 Microchip Technology Inc.
FIGURE 5-1:
Timing Diagrams
1
1
Start
by
Master
Ack
by
TCN75
Address Byte
(a) Typical 2-Byte Read From Preset Pointer Location Such as Temp, T
OS
, T
HYST
(b) Typical Pointer Set Followed by Immediate Read for 2-Byte Register Such as Temp, T
OS
, T
HYST
Ack
by
Master
Most Significant Data Byte
Stop
Cond
by
Master
No Ack
by
Master
Least Significant Data Byte
D7 D6 D5  D4 D3 D2 D1  D0
D7  D6 D5 D4 D3 D2 D1 D0
1  A2  A1  A0 R/W
0   0
1
9
1
9
9
1
1
Start
by
Master
Ack
by
TCN75
Address Byte
Ack
by
TCN75
Pointer Byte
0   0   0   0   0   0  D1  D0
. . . . .
. . . . .
1  A2  A1  A0 R/W
0   0
1
9
9
1
1
Start
by
Master
Ack
by
TCN75T
Address Byte
(c) Typical 1-Byte Read From Configuration Register with Preset Pointer
Data Byte
Stop
Cond
by
Master
No Ack
by
Master
D7 D6 D5 D4 D3 D2 D1  D0
1  A2  A1  A0 R/W
0   0
1
9
9
1
1
Repeat
Start
by
Master
Ack
by
TCN75
Address Byte
Ack
by
Master
Most Significant Data Byte
Stop
Cond
by
Master
No Ack
by
Master
Least Significant Data Byte
D7 D6 D5 D4 D3 D2 D1  D0
D7  D6 D5 D4 D3 D2 D1 D0
1  A2  A1  A0 R/W
0   0
1
9
1
9
9
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